Day 133+1, frequency & throughput

Never one to miss an opportunity to shoehorn an inexplicable reference in where none is required, good evening.

PCI-X input/output is controlled by a phase lock loop to register it to a frequency of 133MHz.  A phased locked loop will be familiar to you if you ever did any background reading on radio communications, anyone with a passing knowledge of 80s CB radio will remember the sales pitch.

"It has a phase lock loop (PLL), and some other shit that you haven't a clue what it is, buy it!"  Etc.

In the CB radio world a PLL was used for frequency synthesis and to generate different frequencies for different channels. The channel frequencies needed to be in exact steps apart and the PLL also provided stability so these didn't drift.  PLL was also used in FM CB for demodulation.

Back to that PCI stuff.  Essentially in the computing world the PLL is used to make sure the frequency doesn't drift and so the PCI bus running at 133MHz can safely transfer data without either the input and output getting out synchronisation and it all ending up in an horrible old mess.

So what about throughput?  Yeah.  The higher the frequency, the greater the throughput of data, in this example at least.





Honestly, I don't know why I climbed on this bicycle, the wheels are too large and the foot clips are too tight.